The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
As semiconductor technologies evolve, chip-scale or chip-size packaging based semiconductor devices have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. In a chip-scale packaging based semiconductor device, the packaging is generated on the die with contacts provided by a variety of bumps. Much higher density can be achieved by employing chip-scale packaging based semiconductor devices. Furthermore, chip-scale packaging based semiconductor devices can achieve smaller form factors, cost-effectiveness, increased performance and lower power consumption.
A chip-scale packaging based semiconductor device may comprise a plurality of solder balls formed on a plurality of under bump metal (UBM) openings of a semiconductor die. The solder balls may be formed of tin and lead. Prior to a reflow process, the semiconductor device is picked and placed on a printed circuit board (PCB) after alignment. As a result, the plurality of solder balls on the chip-scale packaging based semiconductor device are aligned with the corresponding solder pads on the PCB board. By employing a hot air flow and appropriate pressure, the solder balls are heated and then melted so as to connect the semiconductor device with the PCB board. The chip-scale packaging technology has some advantages. One advantageous feature of chip-scale packaging is that chip-scale packaging techniques may reduce fabrication costs. Another advantageous feature of chip-scale packaging based multi-chip semiconductor devices is that parasitic losses are reduced by employing bumps sandwiched between a semiconductor device and a PCB board.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.